1. Field of the Invention
The present invention relates to a sense amplifier circuit for reading data from a memory device such as an E.sup.2 PROM in which, after read data is determined, current flowing through a memory cell is prevented to attain reduction of consuming current.
2. Description of the Prior Art
FIG. 6 is a circuit diagram showing an example of a prior art sense amplifier circuit disclosed in, for example, "LSI Gijyutsu No Kiso (Basic of LSI Technology)" page 179, issued on Jan. 30, 1992 by Denki Tsushin Kyoukai. In the figure, reference numeral 61 denotes a P-channel transistor as a switch for supplying power to the sense amplifier circuit in response to a driving signal supplied through a driving signal input terminal 73 and an inverter 67; 62 and 63 denote P-channel transistors constituting a part of a differential amplifier 66; 64 and 65 denote N-channel transistors constituting another part of the differential amplifier 66; 68 and 69 denote wiring lines which are an input and an output of the differential amplifier 66; 70 denotes a CMOS inverter for inverting the output of the sense amplifier circuit; 71 denotes a data input terminal for inputting data read from a selected memory transistor (hereinafter referred to as a memory cell) 72 through a selected bit line BL into the sense amplifier circuit; and BL (hereinafter written as BL bar) is a bit line connected to a dummy memory cell.
Next, the operation of the circuit shown in FIG. 1 is described. When the driving signal input to the driving signal input terminal 73 at a data read out time is turned to a high level (hereinafter referred to as an H level), the P-channel transistor 61 is turned on through the inverter 67 so that power is supplied to the sense amplifier circuit. Then, depending on whether or not charges are present in a floating gate of the selected memory cell 72 connected to the selected bit line BL, a current I.sub.E flows or does not flow through the bit line BL. To the bit line BL bar, a reference voltage is applied in advance. The differential amplifier 66 amplifies the potential difference between the bit line BL and the bit line BL bar to output read data from this sense amplifier circuit through the output wiring line 69 and the inverter 70.
Since the prior art sense amplifier circuit is constructed as above, the bit line BL is directly connected to the wiring line 68 so that, when charges are present in the floating gate of the selected memory cell 72 and therefore the read out current I.sub.E flows between the drain and the source of the memory cell (that is, when the read out data is at the low level (hereinafter referred to as L level)), the P-channel transistors 61 and 62 are in their on states so that, even after the data read out from the sense amplifier circuit is fixed, the read out current I.sub.E continues to flow from the power supply VDD through the P-channel transistors 61 and 62 and between the drain and the source of the memory cell 72, during operating of the sense amplifier circuit when the driving signal is applied to the driving signal input terminal 73. Accordingly, there is a problem of large consuming current.
Further, when there is no charge in the floating gate of the selected memory cell 72, no read out current I.sub.E flows so that the bit line B1 becomes the H level, however, even after the read out data is fixed, a pseudo write-in current flows from the H level bit line BL to the memory cell 72 during the operation of the sense amplifier circuit so that there is a problem in that, not only the data in the memory cell is damaged, but also the consuming current becomes large.
Still further, the input of the CMOS inverter 70 connected to the output of this sense amplifier circuit is, before the output of the sense amplifier circuit is fixed, at an intermediate level between the H level and the L level, so that a current passes through the CMOS inverter 70, thereby there is a problem of large consuming current.